This invention relates generally to non-volatile memory devices. In particular, the present invention relates to a method and process for manufacturing a non-volatile memory device.
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. The floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating-gate electrode together with the source and drain regions forms an enhancement transistor. By storing electrical charge on the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively high value. Correspondingly, when charge is removed from the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value. The threshold level of the enhancement transistor determines the current flow through the transistor when the transistor is turned on by the application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state. Data resides in a certain logic state on the floating-gate electrode. During a read operation, selected data from a selected floating-gate electrode can be output to an external communication unit using a bit-line.
In a flash EEPROM device, electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating-gate by an overlying control-gate electrode. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied on the control-gate electrode is coupled to the floating-gate electrode. The flash EEPROM device is programmed by applying a high positive voltage to the control-gate electrode, and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating-gate electrode. The flash EEPROM device is erased by grounding the control-gate electrode and applying a high positive voltage through either the source or drain region of the enhancement transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and transferred into either the source or drain regions in the semiconductor substrate.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Many of the foregoing research goals can be addressed through development of materials and processes for the fabrication of the floating-gate electrode. Recently, development efforts have focused on dielectric materials for fabrication of the floating-gate electrode. Silicon nitride in combination with silicon dioxide is known to provide satisfactory dielectric separation between the control-gate electrode and the channel region of the enhancement transistor, while possessing electrical characteristics sufficient to store electrical charge.
One important dielectric material for the fabrication of the floating-gate electrode is an oxide-nitride-oxide (ONO) layer. During programming, electrical charge is transferred from the substrate to the silicon. nitride layer in the ONO layer. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the silicon nitride layer near the source region. Because silicon nitride is not electrically conductive, the charge introduced into the silicon nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in regions within a single continuous silicon nitride layer.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory devices that utilize two regions of stored charge within an ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
While the recent advances in EEPROM technology have enabled memory designers to double the memory capacity of EEPROM arrays using two-bit data storage, numerous challenges exist in the fabrication of material layers within these devices. In particular, fabricating the bit-line oxide region within a memory cell presents several challenges. Traditionally, bit-lines are fabricated using a resist mask, as illustrated in FIGS. 1-5. Referring to FIG. 2, an ONO layer is formed having a first silicon dioxide layer overlying the semiconductor substrate, a silicon nitride layer overlying the first silicon dioxide layer, and a second silicon dioxide layer overlying the silicon nitride layer. A layer of photoresist is then spun on the ONO layer, as illustrated in FIG. 2. The photoresist is then patterned and the semiconductor substrate is doped with a p-type dopant such as boron using ion implantation at a large incidence relative to the principal surface of the semiconductor substrate to allow the p-type implant to be located away from a subsequent n-type dopant, as illustrated in FIG. 3. The wafer is then rotated 180xc2x0 and the semiconductor substrate is doped a second time with a p-type dopant using ion implantation at a large incidence relative to the principal surface of the semiconductor substrate, as illustrated in FIG. 4. Doping the semiconductor substrate with a p-type dopant creates p-type regions, as illustrated in FIGS. 3-4. The exposed ONO layer is then etched to expose part of the semiconductor substrate. The semiconductor substrate is doped with an n-type dopant such as arsenic using ion implantation at an angle substantially normal to the principal surface of the semiconductor substrate, as illustrated in FIG. 5. Doping the semiconductor substrate with n-type dopants creates n-type regions, as illustrated in FIG. 5. Typically, the ONO layer is then etched before the semiconductor substrate is doped with n-type dopants in order to make the implant of n-type dopants a more controlled implant. Once the n-type dopants have been implanted in the semiconductor substrate, the resist mask is stripped and cleaned from the ONO layer and a bit-line oxide region is thermally grown onto the semiconductor substrate, as shown in FIG. 1.
There are several problems that occur with the above described prior art method for fabricating a memory cell. First, it is difficult to pattern the memory cell on a reflective surface with good critical dimension control. Critical dimensions are the widths of the lines and spaces of critical circuit patterns as well as the area of contacts. In order to fabricate memory cells at high density, one needs to be able to pattern with good critical dimension control. Second, it is difficult to accurately control pocket implants or angled implants. When manufacturing the memory cell, pocket implants, such as p-type regions and n-type regions, are formed in the semiconductor substrate. These pocket implants can be created using n-type dopants or p-type dopants and are an essential component of the memory cell. Third, oxidizing structures, such as the bit-line oxide region, at high densities becomes difficult because of the formation of very large bird""s beak structures, as illustrated in FIG. 1. Bird""s beak structures form due to the differences in materials used and affect the critical dimensions of the memory cell, as illustrated by the curving of the ONO layer in FIG. 1. By increasing the distance between memory cells, bird""s beak structures limit the amount of memory cells that can be placed on a two-bit EEPROM device. Fourth, overlay problems occur if the p-type implant and the n-type implant rely on two different masks. Accordingly, advances in memory cell fabrication technology are necessary to insure patterning of high density memory cells used in two-bit EEPROM devices.
The present invention is for a process for fabricating a memory cell in a non-volatile memory device, preferably in a two-bit EEPROM device. Fabrication of a two-bit EEPROM device having a memory cell requires the formation of a high quality bit-line oxide region. This is because proper functionality of the two-bit EEPROM device during a read operation requires selected data from a selected memory cell to be output to an external communication unit. The output of selected data is performed in the bit-line oxide region. In particular, the bit-line oxide region must have good critical dimension control as well as allow for high density devices. High density devices with good critical dimension control are hard to obtain due to the relatively large bird""s beaks that are formed. By fabricating a high quality memory cell having a bit-line oxide region with good critical dimension control, a high-density two-bit EEPROM device can be manufactured.
In one form, a process for fabricating a memory cell includes providing a semiconductor substrate, and forming an ONO layer over the semiconductor substrate. A hard mask is then deposited overlying the ONO layer and patterned. The hard mask comprises a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. The semiconductor substrate is then doped with a p-type dopant such as boron, preferably by using ion implantation. The doping of the semiconductor substrate with a p-type dopant causes p-type regions to form in the semiconductor substrate. The p-type implant can be an angled implant, which is an implant at an angle substantially acute with respect to the principal surface of the semiconductor substrate. Preferably, the p-type implant is a direct implant, which is an implant at an angle substantially normal with respect to the principal surface of the semiconductor surface. If the p-type implant is a direct implant, then the p-type implant can be accomplished in one step and the wafer does not have to be rotated 180xc2x0, as typically required by the prior art. However, if the p-type implant is a direct implant, the semiconductor substrate must be annealed in order for p-type regions to form under the hard mask. Additionally, if the mask is a hard mask, overlay problems can be reduced or nearly eliminated since the p-type implant and the n-type implant can use the same mask.
After doping the semiconductor substrate with p-type dopants, the semiconductor substrate is doped with n-type dopants such as arsenic, preferably by using ion implantation. The n-type implant is a direct implant. The doping of the semiconductor substrate with n-type dopants causes n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate. Once the ONO layer is etched, the hard mask is not removed and a bit-line oxide region is formed overlying the semiconductor substrate. In one preferred embodiment, the ONO layer is etched prior to the n-type implant or the p-type implant. The hard mask acts as a structural member and provides support for the ONO layer during oxidation. By forming the bit-line oxide region with the hard mask still in place, the bit-line oxide region can form with little or no bird""s beak structures. The hard mask is then removed, preferably using a plasma etch process.